1. Field of the Invention
The present invention relates to a semiconductor device structure and its manufacturing method, and more particularly to a manufacturing method for a semiconductor device that uses a dual damascene process in which a metal material is embedded into both a wiring groove and a hole used for the contact between lines.
2. Description of Related Art
Recent years have seen the need for acceleration of semiconductor devices such as LSIs and a trend towards much smaller devices. However, attempts to speed up smaller devices are hampered by line delays. Use of low resist Cu line instead of the conventional Al line is proposed to solve this problem of line delays.
It is difficult to use the dry etching process used when forming Al line on Cu film (or layer) when forming the Cu line. Therefore, the Cu line is formed in a damascene process in which Cu is embedded in a groove provided in an insulation film. The emergence of a dual damascene process in which the metal can be embedded simultaneously in both the wiring groove and in the hole provided for contact between wires means that the number of processes can be reduced compared to the number involved in forming Al line using dry etching. Therefore, the cost of line manufacture can be reduced.
Below, some of the processes involved in the manufacturing method for ordinary semiconductors using the dual damascene process will be briefly explained with reference to FIGS. 24(A)-24(E) through 27.
FIG. 24(A)-24(E) shows the manufacturing processes used for a conventional semiconductor device when the dual damascene process is used. FIG. 24(E) shows a section through the line Ixe2x80x94I on FIG. 27. FIG. 27 is a plan view of the semiconductor device as viewed from above after line has been formed. FIG. 25 is a plan view of the mask used for hole formation and FIG. 26 is a plan view of the mask used for line pattern formation.
Firstly, after a base oxide film 102 is formed on an Si substrate 100, a nitride film 104 is formed on this base oxide film 102. Next, after providing a resist on the nitride film 104, photo lithography is implemented using the mask for hole formation 106 shown in FIG. 25. A hole shaped window 108 is provided in the mask 106. This enables the formation of a resist pattern 110 that corresponds to the hole shape (FIG. 24(A)). This resist pattern 110 is then used as a mask for etching that penetrates the nitride film 104. This enables formation of the hole pattern 112 through the nitride film 104 and exposure of the base oxide film 102 from the hole pattern 112 (FIG. 24(B)). Next, an upper oxide film 114 is provided on the remaining nitride film 104x and the exposed base oxide film 102 (FIG. 24(C)). Then, after a resist has been provided on the upper oxide film 114, the resist undergoes photo lithography processing with the use of the mask 116 for line pattern formation as shown in FIG. 26. This mask 116 is provided with a window 118 in the shape of the wire (or line) pattern. This provides the resist pattern 120. The upper oxide film 114 is then etched using this resist pattern 120 as a mask. Following etching, the remaining nitride film 104x is used as a mask for etching of the base oxide film 102. This forms a contact hole 122 so as to penetrate the base oxide film 102 and to expose the surface of the Si substrate 100. At the same time, a wiring groove 124 in the shape of the line pattern can also be formed (FIG. 24(D)). The wiring metal 126 is next embedded in the contact hole 122 and in the wiring groove 124 using a spatter method or plating (FIGS. 24(E) and 27). The surface of the embedded metal 126 is then flattened using chemo-mechanical polishing (CMP) and polished until it is, in practice, level with the surface of the upper oxide film 114. Thus, the contact between interconnections and the interconnection itself can be formed.
However, the nitride film 104x used as the etching mask used for the base oxide film 102 is generally known to have a high dielectric constant and be highly subject to stress. When the nitride film is made thicker to improve its durability in etching or when it is subject to heat processing in later processes in the manufacture of the semiconductor device, the stress placed on it increases. This causes problems such as cracks in the nitride film or deformation of the hole pattern formed in the nitride film. Also, the thicker the nitride film, the greater the interconnection capacity, the cause of line delays.
Therefore, an object of the present invention is to provide a semiconductor device in which increased interconnection capacity can be prevented and in which the stress that the nitride film is subject to can be limited or decreased. The other object of the present invention is to provide a manufacturing method for semiconductors that avoids the effect of stress on the nitride film during manufacture.
In order to attain the above-mentioned object, the semiconductor device of the present invention has a underlayer, a base oxide film with holes that is formed on this underlayer, a nitride film pattern with a hole pattern that is formed on the base oxide film directly over the holes, an upper oxide film formed on the base oxide film to cover the nitride film pattern, the upper oxide film having formed therethrough a wiring groove wherein part of the nitride film pattern that includes the hole pattern is exposed, and lines that are embedded in the hole and wiring groove. The above nitride film pattern is formed with a shape and size such that its perimeter surrounds the outside of the wiring grooves and does not come into contact with any neighbouring nitride film patterns.
This structure allows the nitride film pattern to be formed with a shape and size that encloses the perimeter of the bottom of the wiring groove. If, in the configuration of the semiconductor device, a plurality of structures with wiring grooves and holes are provided separately, the nitride film pattern is formed with a size and shape that prevents neighbouring nitride film patterns from coming into contact with one another. That is, the perimeter of the nitride film pattern is only slightly larger than the size of the bottom of the wiring groove and therefore much smaller than the total area of the base oxide film. Therefore, the stress placed on the nitride film can be reduced and a semiconductor device made with a low interconnection capacity.